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March 1997
Micro Linear
ML6622* High-Speed Data Quantizer
GENERAL DESCRIPTION
The ML6622 high-speed data quantizer (post-amplifier) is a low noise, wide-band, BiCMOS monolithic IC designed for high-speed signal recovery applications, such as FDDI, Fast Ethernet, and ATM. An internal DC restoration feedback loop nulls any offset voltage produced in the input stage. The limiting amplifier contributes to a high level of sensitivity and a minimum of duty cycle distortion. The output of the data path is a high-speed comparator with ECL outputs. An enable pin gates the comparator on or off in response to the input signal level or a system control signal. The Link Detect circuit provides an Assert-Deassert function with a user-selectable threshold voltage. This circuit monitors the input signal and provides an ECL High output within 100ms of signal acquisition and an ECL Low output within 350ms of signal loss. The ECL discriminator output can be used to disable the comparator when the signal is below the user-selected threshold. LINKLED drives an LED for a visible indication of the link status.
FEATURES
s s s s s
200 MHz bandwidth Low noise design Adjustable Link Detect function Low power design: 35mA typical Used with the ML6633 LED driver
APPLICATIONS
s s s s s
FDDI Fast Ethernet, 100BASE-FX ATM (SONET), 155Mbps Fibre Channel, 133 or 266Mbps Proprietary high-speed fiber optic data links
*Some Packages Are Obsolete
BLOCK DIAGRAM
VCCA 14 VIN+ 13 AMP VIN- 12 ECL CMP GNDA 11 VCC 3 GND 6 4 ECL OUT+ 5 ECL OUT-
FILTER
1 ENABLE
LINK DETECT 7 LINK+ VREF 9 REF THRESH TIMER LINK OUT
8 LINK-
15 CAP
10 THIN
16
2
CTIME LINKLED
Micro Linear
1
ML6622
PIN DESCRIPTION
PIN# 1 NAME ENABLE FUNCTION ECL input active low. When this input is tied to LINKLED the ECL comparator output is automatically enabled and disabled by the Link Detect circuit. This input can be tied to GND for continuous enable. When the ECL Comparator is disabled, ECL OUT- goes low and ECL OUT+ goes high. Link Detect Status output. LINKLED is an open collector active low signal. It will be active low when the input signal applied to VIN+,VIN- exceeds the programmed threshold level at the THIN pin. Capable of driving a 20mA LED indicator. Positive Power Supply. +5 volts Positive and Negative ECL Comparator outputs. 1mA internal pull downs are incorporated. Ground connection. Used for less noise sensitive nodes. Positive ECL Link Detect output. Active high when the input signal exceeds the programmed Link Detect threshold. 1mA internal pull down current sources. Negative ECL Link Detect output. Active low when the input signal exceeds the programmed Link Detect threshold. 1mA internal pull down current sources. A 2.5V reference with respect to GND. NAME PIN # 10 THIN FUNCTION Threshold Input. A voltage applied to this input pin sets the minimum amplitude of the input signal required to cause the link detect to activate. In most cases this can be tied to VREF. Ground connection for noise sensitive circuits in the chip; the input amplifier, DC restoration loop, part of the Comparator and part of the link detect circuit. In some system designs, it may be advantageous to separate GND and GNDA. This input pin should be capacitively coupled to the input source or to VCCA. This input pin should be capacitively coupled to the input source or to VCCA. Positive power supply VCC for noise sensitive circuits as mentioned in GNDA. +5 volts. A capacitor is tied from this pin to VREF. This capacitor sets the lower frequency rejection and helps remove internal DC offset. This capacitor should be 10 times larger than the input capacitors. A capacitor from this pin to ground determines the Link Detect response time. To Meet FDDI specifications this capacitor should be 2,000pF. This capacitor can be removed for faster response time.
11
GNDA
2
LINKLED
12 13 14
VIN- VIN+ VCC A
3
VCC
4 ECL OUT+ 5 ECL OUT- 6 7 GND LINK+
15
CAP
16
8
LINK -
CTIMER
9
V REF
PIN CONNECTION
ML6622 16-Pin Narrow SOIC (S16N)
ENABLE LINKLED VCC ECL OUT+ ECL OUT- GND LINK+ LINK-
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
CTIMER CAP VCCA VIN+ VIN- GNDA THIN VREF
TOP VIEW
2
Micro Linear
ML6622
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC ....................................................... GND -0.3V to 6V VCCA ..................................................... GND -0.3V to 6V Inputs/Outputs .......................... GND - 0.3V to VCC + 0.3 Junction Temperature ............................................. 150C Storage Temperature Range ...................... -65C to 150C Lead Temperature (Soldering 10 sec.) ...................... 260C Thermal Resistance ........................................... 100C/W
ELECTRICAL CHARACTERISTICS
SYMBOL ICC VREF IVREF VIN VTH ADJ Range EN RIN ITHIN VOL-VCC VOH-VCC PARAMETER VCC Supply Current Reference Voltage VREF Output Current Input Signal Range External Voltage at THIN to set VTH Input-referred Voltage Noise Input Resistance Input Bias Current of THIN ECL Output Voltage-Low ECL Output Voltage-High
Unless otherwise specified, VCC = V CC = 5V 10%, TA = Operating Temperature Range. (Note 1)
CONDITIONS No load on ECL outputs 2.30 -1 3.5 0.5 100 MHz BW VIN+, VIN- 500 -100 Through 50 to VCC -2V Through 50 to VCC -2V C Suffix I Suffix tr tf Link Detect AS_Max ANS_Max VTH BW VIPW DCD DDJ
Note 1:
MIN
TYP 35 2.47 3
MAX 50 2.57 +5 1600 VREF
UNITS mA V mA mVP-P V VRMS
25 770 1500 +100 -1.730 -0.963 -0.963 -1.620 -0.800 -0.780 1.3 1.3
A V V V ns ns
-1.810 -1.025 -1.025 0.5 0.5
Data Output Rise Time Data Output Fall Time
Assert Time (off to on) Deassert Time (on to off) Input threshold Hysteresis Bandwidth 1-3dB Minimum Input Pulse Width Duty Cycle Distortion Peak-to-peak Data Dependent Jitter Peak-to-peak
CTIME = 2000pF CTIME = 2000pF THIN = VREF Assert
0 0 8 1.5 10 1.7 200 5
100 350 12 2
s s mV dB MHz ns ns ns
Data rate = 155Mb/s 50% duty cycle input FDDI - 56 Data Pattern VIN = 60mV, Data rate = 125Mb/s
0.5 1.2
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case conditions.
Micro Linear
3
ML6622
FUNCTIONAL DESCRIPTION
The ML6622 high speed data quantizer accepts a low level analog signal from a pin diode and transimpedance amp front end and converts it into digital ECL levels for subsequent digital processing. The input signal, from a transimpedance amplifier, is immediately amplified by a two-stage video amplifier. The output of this amplifier feeds two parallel paths. The data path is comprised of a high speed comparator that outputs PECL differential data on the ECL OUT pins. The Link Detection path monitors the magnitude of the amplified input signal, compares it to a user-settable threshold, and provides the result of the comparison as a PECL differential output on the Link pins. The timer following the threshold block is used to set the Link Detect output acquire and deacquire time using a capacitor. AMPLIFIER The amplifier is a two stage video amplifier with a gain of approximately 55V/V. Maximum sensitivity is achieved through the use of the DC restoration feedback loop and AC coupling the input. The AC coupling input capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with the lower 3dB point determined by the input resistance and the input coupling capacitors. This cap also adds a secondary pole to the offset loop. Since the amplifier has a differential input, two AC capacitors of equal value are required. If the signal driving the input is single ended, the other coupling capacitor should be tied to VCC . A low-pass filter in the offset loop is created with the capacitor on pin 15 (CAP). The lower 3dB point controlled by a capacitor tied from the CAP pin to VREF as shown in the application circuit. For stability reasons the value of the capacitor on the CAP pin should be 10 times larger than the input coupling capacitors. The 3dB point is given by the following equation: F3dB 1 = 2 x 100k x C COMPARATOR A high speed ECL comparator with PECL outputs is used for the quantization function. The comparator has an Enable input pin which takes an ECL level. This Enable pin is normally driven by LINKLED, which causes the output to be enabled when the link is up and disabled when the link is down. When ENABLE is low the comparator is operational. When ENABLE is high the comparator is disabled causing ECL OUT- to go low and ECL OUT+ to go high. The ENABLE pin can be tied to ground to keep the comparator permanently enabled. LINK DETECT CIRCUIT The Link Detection Circuit is used to accurately measure the input amplitude to determine whether it is large enough to reliably recover the input signal. Once the Bit Error Rate (BER) for the ML6622 receive circuit is determined, the link detect threshold can be set so that the Link Detect Circuit will shut off before the error rate exceeds the link requirement. The Link Detection Circuit consists of three functional blocks; Thresh, Timer, and Link Out. Thresh detects the output of Amp and compares it to a programmable threshold input THIN. As long as the input amptitude is greater than the programmable threshold input, the Link Detect output remains active. When the peak input drops below THIN, Thresh's output changes state and Timer delays the Link Out state change for a programmable amount of time. When using the default CTIME capacitance of 2000pF, the deassert time and the assert time values conform to the ANSI X3.1661990 PMD standard for FDDI. To improve stability, the Link Detect circuit includes 1.7dB of hysteresis. The VREF output can be tied directly to THIN to set the Link Detect threshold. For greater sensitivities, VREF can be divided down before applied to THIN. The formula for the threshold on the thin pin is as follows: Threshold(Assert) = VTHIN 500 VTHIN 750
Although the input is AC coupled, the offset voltage within the amplifier will be present at the amplifier's output. The removal of the dc offset in the amplifier helps the circuit respond to small input voltages, and reduces duty-cycle distortion. In order to reduce this error, a negative feedback loop nulls the offset voltage. An external capacitor connected to the CAP pin is used to store the offset voltage. This voltage is compared to VREF and a difference current proportional to the result is applied to the negative side of the input stage of the AMP circuit block thereby nulling the DC offset.
Threshold(Deassert) =
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Micro Linear
ML6622
APPLICATION CIRCUIT
+5V 1 470 2 OPTIONAL +5V 3 4 1K 5 1K 6 7 1K 8 1K LINK- VREF 9 GND LINK+ GNDA 11 THIN 10 VRF- ECL OUT- LINKLED VCC ECL OUT+ CAP 15 VCCA 14 VIN+ 13 VIN- 12 ENABLE CTIMER 16 VRF- 0.1F
VRF+ 0.01F 0.01F VRF+
4.7H +5V .1 +4.7 4.7H +4.7 .1 VRF- OPTIONAL VRF+
Micro Linear
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ML6622
PHYSICAL DIMENSIONS inches (millimeters)
Package: S16N 16-Pin Narrow SOIC
0.386 - 0.396 (9.80 - 10.06) 16
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
ORDERING INFORMATION
PART NUMBER ML6622CS ML6622IS TEMPERATURE RANGE 0 to 70C -40 to 85C PACKAGE 16-Pin Narrow SOIC (S16N) 16-Pin Narrow SOIC (S16N) (Obsolete)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS6622-01
6
Micro Linear

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